The present invention generally relates to a method for forming solder bumps on flip chips and devices formed, and more particulary, relates to a method for forming fine-pitched solder bumps on flip chips by a dual-photoresist method in which a thin photoresist is first used to define the solder bumps on a BLM (ball-limiting-metallurgy) layer and then a thick photoresist layer is used for defining the height of the solder bumps so that the accuracy for placement of the solder bumps can be greatly improved and devices formed by the method.
In the fabrication of modem semiconductor devices, the ever increasing device density and decreasing device dimensions demand more stringent requirements in the packaging or interconnecting techniques of such high density devices. Conventionally, a flip-chip attachment method has been used in packaging of semiconductor chips. In the flip-chip attachment method, instead of attaching a semiconductor die to a lead frame in a package, an array of solder bumps is formed on the surface of the die. The formation of the solder bumps may be carried out in an evaporation method by using a composite material of tin and lead through a mask for producing a desired pattern of solder bumps. The technique of electrodeposition has been more recently developed to produce solder bumps in flip-chip packaging process.
Other techniques that are capable of solder-bumping a variety of substrates to form solder balls have also been proposed. The techniques generally work well in bumping semiconductor substrates that contain solder structures over a minimal size. For instance, one of such widely used techniques is a solder paste screening method which has been used to cover the entire area of an eight inch wafer. However, with recent trend in the miniaturization of device dimensions and the necessary reduction in bump-to-bump spacing (or pitch), the use of the solder paste screening technique has become impractical for several reasons. One of the problems in utilizing solder paste screening technique in bonding modem semiconductor devices is the paste composition itself. A solder paste is formed by a flux material and solder alloy particles. The consistency and uniformity of the solder paste composition become more difficult to control as the solder bump volume decreases. Even though a solution of the problem has been proposed by using solder paste that contain extremely small and uniform solder particles, it can only be achieved at a high cost penalty. A second problem in utilizing the solder paste screening technique in modem high density semiconductor devices is the available space between solder bumps. It is known that a large volume reduction occurs when a solder changes from a paste state to a cured stated, the screen holes for the solder paste must be significantly larger in diameter than the actual solder bumps to be formed. The large volume shrinkage ratio thus makes the solder paste screening technique difficult to carry out in high density devices.
Other techniques for forming solder bumps such as the controlled collapse chip connection (C4) technique and the thin film electrodeposition technique have also been used in recent years in the semiconductor fabrication industry. The C4 technique is generally limited by the resolution achievable by a molybdenum mask which is necessary for the process. Fine-pitched solder bumps are therefore difficult to be fabricated by the C4 technique. Similarly, the thin film electrodeposition technique which also requires a ball limiting metallurgy layer to be deposited and defined by an etching process which has the same limitations as the C4 technique. For instance, a conventional thin film electrodeposition process for depositing solder bumps is shown in FIGS. 1Axcx9c1F.
A conventional semiconductor structure 10 is shown in FIG. 1A. The semiconductor structure 10 is built on a silicon substrate 12 with active devices built therein. A bond pad 14 is formed on a top surface 16 of the substrate 12 for making electrical connections to the outside circuits. The bond pad 14 is normally formed of a conductive metal such as aluminum. The bond pad 14 is passivated by a final passivation layer 20 with a window 22 opened by a photolithography process to allow electrical connection to be made to the bond pad 14. The passivation layer 20 may be formed of any one of various insulating materials such as oxide, nitride or organic materials. The passivation layer 20 is applied on top of the semiconductor device 10 to provide both planarization and physical protection of the circuits formed on the device 10.
Onto the top surface 24 of the passivation layer 20 and the exposed top surface 18 of the bond pad 14, is then deposited an under bump metallurgy layer 26. This is shown in FIG. 1B. The under bump metallurgy (UBM) layer 26 normally consists of an adhesion diffusion barrier layer 30 and a wetting layer 28. The adhesion diffusion barrier layer 30 may be formed of Ti, TiW or other metal such as Cr. The wetting layer 28 is normally formed of a Cu layer or a Ni layer. The UBM layer 26 improves bonding between a solder ball to be formed and the top surface 18 of the bond pad 14.
In the next step of the process, as shown in FIG. 1C, a photoresist layer 34 is deposited on top of the UBM layer 26 and then patterned to define a window opening 38 for the solder ball to be subsequently formed. In the following electrodeposition process, a solder ball 40 is electrodeposited into the window opening 38 forming a structure protruded from the top surface 42 of the photoresist layer 34. The use of the photoresist layer 34 must be carefully controlled such that its thickness is in the range between about 30 xcexcm and about 40 xcexcm, preferably at a thickness of about 35 xcexcm. The reason for the tight control on the thickness of the photoresist layer 34 is that, for achieving a fine-pitched solder bump formation, a photoresist layer of a reasonably small thickness must be used such that a high imaging resolution can be achieved. It is known that, during a photolithography process, the thicker the photoresist layer, the poorer is the imaging process. To maintain a reasonable accuracy in the imaging process on the photoresist layer 34, a reasonably thin photoresist layer 34 must be used which results in a mushroom configuration of the solder bump 40 deposited therein. The mushroom configuration of the solder bump 40 contributes greatly to the inability of a conventional process in producing fine-pitched solder bumps.
Referring now to FIG. 1E, wherein the conventional semiconductor structure 10 is shown with the photoresist layer 34 removed in a wet stripping process. The mushroom-shaped solder bump 40 remains while the under bump metallurgy layer 26 is also intact. In the next step of the process, as shown in FIG. 1F, the UBM layer 26 is etched away by using the solder bump 40 as a mask in an wet etching process. The solder bump 40 is then heated in a reflow process to form solder ball 44. The reflow process is conducted at a temperature that is at least the reflow temperature of the solder material.
The conventional method for depositing solder bumps described above presents a number of processing difficulties. For instance, one of the difficulties is the large volume of solder used in a mushroom-shaped bump which impedes the process of making fine-pitched bumps. By fine-pitched bumps, it is meant that the distance maintained between the bases of the bumps is less than 150 xcexcm, and preferably less than 120 xcexcm. In a conventional method, the solder bumps are planted before a BLM layer deposited under the bumps is removed, i.e., the BLM layer is not patterned prior to the solder bump planting step. A BLM layer removal process after the bumps are planted in place such as a wet etching process is therefore necessary. When fine-pitched bumps are planted such that little spaces are left between the bumps, a complete removal of the BLM layer between the bumps becomes difficult. An extended length of time for the etching process is therefore necessary which leads to possible attacks on the solder bumps by the etchant and possible oxidation of the bumps. Another drawback of the conventional fine-pitched bump planting process is the necessity of using a thick photoresist layer in order to achieve the height of the bumps. It is known in photolithography that the thicker the photoresist layer used, the more difficult it is to achieve high accuracy in the imaging of the pattern in the photoresist layer due to focusing difficulties. Poor accuracy in the imaging process leads to misplacement of the solder bumps in relation to the positions of the bond pads. Serious reliability problems may result when the aluminum bonding pads are not completely covered by the solder bumps. The conventional method for planting fine-pitched solder bumps therefore leaves much to be desired and does not provide solder bumps of high quality and reliability.
It is therefore an object of the present invention to provide a method for forming fine-pitched solder bumps on flip chips that does not have the drawbacks or shortcomings of the conventional methods.
It is another object of the present invention to provide a method for forming fine-pitched solder bumps on flip chips by utilizing at least two photolithographic processes.
It is a further object of the present invention to provide a method for forming fine-pitched solder bumps on flip chips by first defining a BLM layer prior to the planting of solder bumps.
It is another further object of the present invention to provide a method for forming fine-pitched solder bumps on flip chips wherein the bump-to-bump distance may by smaller than 120 xcexcm.
It is still another object of the present invention to provide a dual-photoresist method for forming fine-pitched solder bumps on flip chips by first using a thin photoresist layer to pattern a BLM layer and then using a thick photoresist layer to define window openings for the solder bumps.
It is yet another object of the present invention to provide a dual-photoresist method for forming fine-pitched solder bumps on flip chips wherein a BLM layer coated between the bumps can be thoroughly removed by a wet etching process.
It is still another further object of the present invention to provide a dual-photoresist method for forming fine-pitched solder bumps on flip chips wherein a non-leachable metal layer such as Cu or Ni is first deposited on top of an etched BLM layer prior to the planting of the solder bumps for use as an electrode layer during the electroplating process.
It is yet another further object of the present invention to provide solder bumps that are formed on a flip chip wherein the solder bumps are joined to a BLM layer with an interface thereinbetween comprising atoms of a non-leachable metal such as Cu or Ni.
In accordance with the present invention, a method for forming fine-pitched solder bumps on flip chips and devices formed by such a method are disclosed.
In a preferred embodiment, a dual-photoresist method for forming fine-pitched solder bumps on flip chips may be carried out by the operating steps of providing an electronic substrate which has a bond pad formed on top, the bond pad is embedded in an insulating layer with only a top surface exposed, depositing a BLM layer on top of the electronic substrate, coating a first photoresist layer on top of the BLM layer, the first photoresist layer has a first thickness that is sufficiently small such that an exposure accuracy of a least xc2x12 xcexcm can be achieved, etching the first layer of BLM layer away except areas over the bond pads, coating a second photoresist layer on top of the etched BLM layer, the second photoresist layer has a second thickness that is larger than the first thickness, forming a via opening in the second photoresist layer over the BLM layer and filling with a solder to form a solder bump, and removing the second photoresist layer and reflowing the solder bump into a solder ball.
The dual-photoresist method for forming fine-pitched solder bumps on flip chips may further include the step of depositing a none-leachable metal layer on top of the etched BLM layer prior to the coating step for the second photoresist layer, the non-leachable metal does not leach into a solder bump material that is subsequently deposited on top. The non-leachable metal layer may be formed of a metal that has high electrical conductivity. The non-leachable metal layer may be deposited of a material selected from the group consisting of Cu and Ni. The non-leachable metal layer may be deposited to a thickness of not more than 1 xcexcm, to a thickness between about 0.01 xcexcm and about 1 xcexcm, or preferably to a thickness between 0.05 xcexcm and 0.3 xcexcm. The electronic substrate may be a silicon wafer.
In the dual-photoresist method for forming fine-pitched solder bumps on flip chips, the BLM layer may include at least two sublayers selected from the group consisting of an adhesion sublayer, a barrier sublayer and a bonding sublayer. The adhesion sublayer may be formed of a metal such as Cr or Ti, the barrier sublayer may be formed of a metal such as Cu, Pd, Pt or Ni, and the bonding sublayer may be formed of a metal such as Au and Pt. The first thickness of the first photoresist layer may be not more than 10 xcexcm, and preferably between about 2 xcexcm and about 5 xcexcm. The second thickness of the second photoresist layer is substantially similar to the height of the solder bumps planted in the via opening formed in the second photoresist layer. The second thickness of the second photoresist layer may be sufficient to a solder ball after reflow to a thickness of not less than 50 xcexcm. The step of filling the via opening with a solder may be carried out by a method of either electroplating.
In an alternate embodiment, a method for forming fine-pitched solder bumps on a silicon wafer may be carried out by the operating steps of first providing a silicon wafer that has a multiplicity of bond pads formed on top, then depositing a BLM layer on top of the multiplicity of bond pads, then coating and patterning a first photoresist layer on top of the BLM layer, the first photoresist layer is coated to a thickness not more than 10 xcexcm, etching the BLM layer away except on top of the multiplicity of bond pads, coating and patterning a second photoresist layer on top of the etched BLM layer, the second photoresist layer is coated to a thickness of at least 50 xcexcm, defining and forming a multiplicity of via opening in the second photoresist layer to expose the multiplicity of bond pads, filling the multiplicity of via opening with a solder material to form a multiplicity of solder bumps, and removing the second photoresist layer.
The method for forming fine-pitched solder bumps on a silicon wafer may further include the step of reflowing the multiplicity of solder bumps into a multiplicity of solder balls. The method may further include the step of depositing a non-leachable layer on top of the etched BLM layer prior to the coating of the second photoresist layer. The non-leachable metal is defined as a metal that does not leach into a solder bump material which is subsequently deposited on top of the non-leachable metal layer. The non-leachable metal layer may be deposited of Cu or Ni to a thickness of not more than 1 xcexcm. The non-leachable metal layer may be deposited to a thickness between about 0.01 xcexcm and 1 xcexcm, and preferably between about 0.05 xcexcm and about 0.3 xcexcm.
The present invention is further direct to a solder ball that is formed on a silicon wafer which includes a pre-processed silicon wafer which has a top surface, a bond pad on the top surface, a BLM layer on the bond pad, and a solder ball integrally joined to the BLM layer with an interface thereinbetween, the interface includes atoms of a non-leachable metal of Cu or Ni.
In the solder ball formed on a silicon wafer, the BLM layer may further include an adhesion layer and a diffusion barrier layer. The BLM layer may be selected from the group consisting of Ti/Cu, TiW/Cu, Cr/Ni, Al/Nixe2x80x94V/Cu and Cr/CrCu/Cu/Au. The solder ball may include Sn and Pb.